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ICs for Telephone
AN6472NFBP
Cordless Telephone Speech Network IC Incorporating Cross-Point Switch
s Overview
The AN6472NFBP is a speech network IC which includes a receiver noise reducing function and is most suitable for quality cordless telephones. It incorporates a cross-point switch controlled by serial input. It allows speech path switching and mixing, and provides for three- or four-person communication and other sophisticated functions. It also incorporates REC/PLAY amplifiers with VOX circuits.
64 1 49 0.8 0.350.1 14.00.3 17.20.4 0.15 -0.05 1.30.25 1.30.25 2.80.2 0.55 14.00.3 17.20.4 QFP package with 64 pins (QFH064-P-1414)
+0.1
Unit : mm
48
16 17 32
33
s Features
* The speech block can operate on line voltage, with no external power supply, and is operational even during a commercial power failure. * Incorporates a receiver noise reducing function to improve the handset's howling margin. * Incorporates auto. PAD, dial mute, DC voltage regulation, and other basic speech functions. * The cross-point switch can be operated independently. * Each output of the cross-point switch can correspond to multiple inputs, allowing three- or four-person communication. * The REC/PLAY amplifiers incorporate ALC and VOX circuits. * Receiver volume can be increased by 6 dB or 9 dB.
0.10.1
1
AN6472NFBP
s Block Diagram
ICs for Telephone
48
47
46
45
44
43
42
41 ALC Det.
40
39
38
37 VOX Det.
36
35
34
33 32
49
L(OF)
- + L(07)
- +
0dB
0dB
COMP
31
50
VREF
10dB
ALC INJ 30
GND
51 52
+ 0dB
53 54
-
0/12 dB
20 dB
18 dB
18 dB
29 28
GND
+
55 56
-
D Latch
6dB
27 26 25 DC Control DM Control L(3F)
+
Decoder
a1 a2 a3 a4 a5 a6
57
0dB
24 23 22 21
58
0dB
59 Power Supply Control 60 61 62 63
DCC AP P.O.R Line Supply Monitor
0dB DMC 0dB DMC 0dB VCC 0dB 0dB
0dB
-
20
- DMC +
AP Noise Protection DMC L(17) L(1F)
+ 30dB -
VCC 0dB
19 18 17
VREF 64
AP Control
Det.
0/6/9dB L(27)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
2
ICs for Telephone
s Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Ground Line power (+) input Side-tone adjustment Line voltage control (1) Int. ref. voltage output (2) Int. ref. voltage output (1) Trans. preamp. output Noise reduction detection output Noise reduction detection input Noise reduction amp. output Auto. PAD control Rec. preamp. input Rec. preamp. output Rec. amp. input Rec. amp. output (1) Rec. amp. output (2) BT signal input DTMF preamp. output DTMF signal input MIC preamp. output MIC preamp. input (1) MIC preamp. input (2) Dial mute control Line voltage control Line interruption detector output Strobe signal input Clock signal input Data input Ground Logic power supply input VOX detector output SP link output Description Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 RF2 link output RF1 link output Intercom link output VOX detection control VOX amp. input Time stamp link output Recording link output ALC input ALC detection control Loudspeaker link input Recording input Recording inverse input Recording preamp. output Recording bias current control To recording head EQ amp. inverse input EQ amp. output REC/PLAY int. ref. voltage output Ground MIX preamp. output MIX link input AUX preamp. output AUX link input Intercom link input RF1 link input RF2 link input Power-ON reset control External supply voltage input Internal supply voltage output Circuit voltage control (2) Line current bypass (2) Line current bypass (1) Description
AN6472NFBP
s Absolute Maximum Ratings (Ta=25C)
Parameter Supply voltage (1) Supply current (1) Supply voltage (2) Supply current (2) Power dissipation*1 Operating ambient temperature Storage temperature *1 In a free-air condition with Ta=75C Symbol VCC ICC VL IL PD Topr Tstg Rating 7.0 50 12.0 135 640 -20 to+75 -55 to+150 Unit V mA V mA mW C C
3
AN6472NFBP
s Recommended Operating Range
Parameter Operating supply voltage range (1) Operating supply voltage range (2) Symbol VCC VL Range 4.5V to 5.5V 3.0V to 11.0V
ICs for Telephone
s Recommended Operating Conditions (Ta =20 to +75C)
Parameter Supply voltage Clock frequency Input pulse width Setup time Hold time Input pulse width (high) Input pulse width (low) Clock pulse rise time Clock pulse fall time Input voltage CLK STB DATA STB DATA STB Symbol VCC fCLK tW tsu th twh twl tr tr Vi 0 Input Duty 40% to 50% 1.6 1.2 1.6 0.8 1.6 1.2 0.8 0.8 20 20 VCC Condition min 4.5 typ 5 max 5.5 250 Unit V kHz s s s s s s s s s s V
s Electrical Characteristics (Ta=252C)
Parameter Symbol Condition V-DCC=HIGH, IL=20mA, VCC=0V V-DCC=HIGH, IL=60mA, VCC= 0V V-DCC=HIGH, IL=120mA, VCC= 0V V-DCC= LOW, IL=30mA, VCC= 0V V-DCC= LOW, IL= 60mA, VCC= 0V V-DCC= LOW, IL=120mA, VCC= 0V V- DCC=HIGH, IL=20mA, VCC= 0V V-DCC=HIGH, IL=20mA, VCC= 0V V- DCC=HIGH, IL=20mA, VCC=5V V-DCC=HIGH, IL=20mA, VCC=5V V-DCC=HIGH, IL=20mA, VCC=5V V-DCC=HIGH, IL=20mA, VCC=5V min typ max Unit Power Supply Characteristics During Power Failure Line DC voltage (I-1) Line DC voltage (I-2) Line DC voltage (I-3) Line DC voltage H (I-1) Line DC voltage H (I-2) Line DC voltage H (I-3) Internal supply voltage (I) Internal ref. supply voltage (I) Normal power supply characteristics Line DC voltage (E-1) Line DC voltage (E-2) Line DC voltage (E-3) Line DC voltage H (E-1) VL - E1 VL - E2 VL - E3 VLH - E1 3.1 4.3 6.3 4.3 3.4 4.7 6.8 4.85 3.8 5.1 7.3 5.4 V V V V VL - I1 VL - I2 VL - I3 VLH - I1 VLH - I2 VLH - I3 Vreg - I Vref - I 3.2 4.5 6.6 4.5 5.7 7.9 1.8 0.9 3.5 4.8 7.0 5.0 6.2 8.5 2.0 1.0 3.8 5.2 7.5 5.5 6.7 9.2 2.2 1.1 V V V V V V V V
4
ICs for Telephone
s Electrical Characteristics (cont.) (Ta=252C)
Parameter Line DC voltage H (E-2) Line DC voltage H (E-3) Internal supply voltage (E) Internal ref. supply voltage (E) Total circuit current Power interruption detection (1) Power interruption detection (2) Receiver During Power Failure Rec. gain (I-1) Rec. gain (I-2) Rec. auto. PAD width (I)*1 Rec. max. output (I) Rec. noise reduction (I) GV - IR1 GV - IR2 AP - IR VO - IR NL - IR IL=30mA, VCC= 0V Vin= - 42dBm IL= 80mA, VCC= 0V Vin= -42dBm IL=30mA- 80mA, VCC= 0V, Vin= - 42dBm With IL=30mA, VCC= 0V, and THD=5% IL=30mA, VCC= 0V, Vin= -42dBm Vin-M= -65/-50dBm IL=30mA, VCC= 0V, V-DMC=LOW, Vin= -30dBm IL=30mA, VCC=5V Vin= -42dBm IL=30mA, VCC=5V Vin= -42dBm IL=30mA-80mA, VCC=5V Vin= -42dBm With IL=30mA, VCC=5V, and THD=5% IL=30mA, VCC=5V, Vin= -42dBm Vin-M= -65/-65dBm IL=30mA, VCC=5V, Vin= -42dBm, DV-1 ON IL=30mA, VCC=5V, Vin= -42dBm, DV-2 ON IL=30mA, VCC=5V, V-DMC=LOW, Vin= -30dBm For VCC=0V and 5V(between Gv-IR1 and Gv-ER1) R=27(Pin3), IL=30mA, VCC=0V, Vin= -38dBm IL=80mA, VCC=0V, Vin= -38dBm IL=30mA-80mA, VCC=0V, Vin= -38dBm 30.5 27 2.5 0 4 Symbol VLH - E2 VLH - E3 Vreg - E Vref - E Itotal V - HIT1 V - HIT2 Condition V-DCC=LOW, IL=60mA, VCC=5V V-DCC=LOW, IL=120mA, VCC=5V V-DCC=HIGH, IL=20mA, VCC=5V V-DCC=HIGH, IL=20mA, VCC=5V V-DCC=HIGH, IL=20mA, VCC=5V VL=2.7V, VCC=5V VL=1.5V, VCC=5V min 5.3 7.55 4.6 2.25 17 0 4.4 typ
AN6472NFBP
max 6.6 8.9 5.0 2.7 35 0.6 5
Unit V V V V mA V V
5.95 8.2 4.85 2.5 27 0.1 4.95
32.5 29 3.5 4 6
34.5 31 5
dB dB dB dBm
8
dB
BT amp. gain (I) Receiver On External Power Supply Rec. gain (E-1) Rec. gain (E-2) Rec. auto. PAD width (E)*1 Rec. max. output (E) Rec. noise reduction (E) Rec. digital volume (1)*2 Rec. digital volume (2)*2 BT amp. gain (E) Rec. gain difference Transmitter Amp. During Power Failure Trans. gain (I-1) Trans. gain (I-2) Trans. auto. PAD width (I)*1
GV - IBT
19
21
23
dB
GV - ER1 GV - ER2 AP - ER VO - ER NL - ER GV - DV1 GV - DV2 GV - EBT DG-R
30.5 26.8 2.5 4 6 5 7.5 19.5 -1.2
32.5 28.8 3.7 12 8 6 9 21.5 - 0.1
34.5 30.8 5
dB dB dB dBm
10 7 10.5 23.5 1.2
dB dB dB dB dB
GV - IM1 GV - IM2 AP - IM
28.2 24.4 2.5
30.2 26.4 3.8
32.2 28.4 5
dB dB dB
Note) Unless otherwise specified, input signal Fin =1kHz, control voltage V-DOC = high, and control voltage V-DMC = high. *1 Gain decrease when line current IL is changed from 30 to 80 mA. If pin 11 (auto. PAD control)is connected to pin 61 (int. supply voltage output), the gain will not change. *2 Gain increase from receiver gain (E-1).
5
AN6472NFBP
s Electrical Characteristics (cont.) (Ta=252C)
Parameter Trans. max. output (I-1) Trans. max. output (I-2) DTMF gain (I-1) Symbol VO - IM1 VO - IM2 GV - ID1 Condition With IL=30mA, VCC= 0V and HD=5% With IL=30mA, VCC= 0V, THD=5% and V-DCC=LOW IL=30mA, VCC= 0V, V-DMC= LOW, Vin= -30dBm IL=80mA, VCC= 0V, V-DMC=LOW, Vin= -30dBm IL=30mA-80mA, VCC= 0V, V-DMC= LOW, Vin= -30dBm IL=30mA, VCC=0V, V-DMC=LOW, THD=5% IL=30mA, VCC= 0V, THD=5%, V-DMC=LOW, V-DCC=LOW IL=30mA, VCC= 0V, Vin= -38dBm IL=80mA, VCC=5V, Vin= -38dBm IL=30mA-80mA, VCC=5V, Vin= -38dBm With IL=30mA, VCC=5V and THD=5% IL=30mA, VCC=5V, THD=5%, V-DCC=LOW IL=30mA, VCC=5V, DM=ON, Vin= -30dBm IL=80mA, VCC=5V, V-DMC=LOW, Vin= -30dBm IL=30mA-80mA, VCC=5V, V-DMC=LOW, Vin= -30dBm IL=30mA, VCC=5V, V-DMC=LOW, THD=5% IL=30mA, VCC=5V, DM=ON, V-DMC=LOW, THD=5% For VCC= 0V and VCC=5V (between Gv-IM1 and Gv-EM1) For VCC= 0V and 5V (between Gv-ID1 and Gv-ED1) min 0 0 17.5
ICs for Telephone
typ 3.5 3.5 19.5
max
Unit dBm dBm
21.5
dB
DTMF gain (I-2)
GV - ID2
13.7
15.7
17.7
dB
DTMF auto. PAD width (I)*1 DTMF max. output (I-1) DTMF max. output (I-2)
AP - IDT VO - ID1 VO - ID2
2.5 0 0
3.8 3.8 3.5
5
dB dBm dBm
Transmitter Amp. On External Power Supply Trans. gain (E-1) Trans. gain (E-2) Trans. auto. PAD width (E)*1 Trans. max. output (E-1) Trans. max. output (E-2) DTMF gain (E-1) DTMF gain (E-2) GV - EM1 GV - EM2 AP - EM VO - EM1 VO - EM2 GV - ED1 GV - ED2 28.6 25.0 2.5 2 2 18.1 14.5 30.6 27.0 4 6 6 20.1 16.5 22.1 18.5 32.6 29.0 5 dB dB dB dBm dBm dB dB
DTMF auto. PAD width (E)*1 DTMF max. output (E-1) DTMF max. output (E-2) Trans. gain difference DTMF gain difference
AP - EDT VO - ED1 VO - ED2 DG - M DG - MF
2.5 2 2 -1.8 -2.3
4.1 6 6 -0.8 -1.3
5.5
dB dBm dBm
0.7 0.2
dB dB
Note) Unless otherwise specified, input signal Fin=1 kHz, control voltage V-DOC=high, and control voltage V-DMC=high. *1 Gain decrease when line current IL is changed from 30 to 80 mA. If pin 11 (auto. PAD control) is connected to pin 61(int. supply voltage output) , the gain will not change.
6
ICs for Telephone
s Electrical Characteristics (cont.) (Ta=252C)
Parameter Recording Preamplifiers Rec. preamp. gain Rec. preamp. output Rec. preamp. output noise voltage*1 Recording Amplifier Head bias current Head output Playing EQ Amplifier EQ amp. gain EQ amp. output noise voltage VOX Detector VOX sensitivity (1) VOX sensitivity (2) Link SW Input Amplifier MIX amp. gain AUX amp. gain Link SW Output Amplifier SP output gain (1)*1 SP output gain (2)*1 Intercom output gain*1 RF1 output gain*1 RF2 output gain*1 Recording output gain*1 Recording output gain*1 Line output gain*1 Rec. output gain difference*2 Time stamp output gain*1 GV - SPO1 GV - SPO2 GV - DHO GV - RF10 GV - RF20 GV - RECO GV - RO GV - TO GD - RO GV - TSO Input AUX IN, Vin= - 36dBm, L-SW (h3A) = ON Input AUX IN, Vin= - 36dBm, L-SW (h3A&h2F) = ON Input AUX IN, Vin= - 36dBm, L-SW (h3B) = ON Input AUX IN, Vin= - 36dBm, L-SW (h3C) = ON Input AUX IN, Vin= - 36dBm, L-SW (h3D) = ON Input AUX IN, Vin= - 36dBm, L-SW (h3E) = ON Input AUX IN, Vin= - 36dBm, L-SW (h38) = ON Input AUX IN, Vin= - 36dBm, L-SW (h39) = ON Input AUX IN, Vin= - 36dBm, L-SW (h30) = ON Input AUX IN, Vin= - 36dBm, L-SW (h37) = ON 11 -1.5 18.5 16.5 16.5 -1.0 19.9 17.7 -1.0 -1.0 GV - MIX GV - AUX Vin= - 36dBm Vin= - 36dBm 5 5 VS1 VS2 I-VOX=12.5A I-VOX=24.5A 3.5 GV - EQ Vno - EQ L-SW (h07)= ON, Vin= - 40dBm L-SW (h07)= ON, DIN/AUDIO, RL=1k 27.8 I - REC GV - REC L-SW (h07)= ON L-SW (h07)= ON, Vin= -15dBm, RL=1k 145 40.0 GV - Rp VO - RP Vno - RP Vin= - 60dBm, Rin=0 Vin= - 45dBm, Rin=10 DIN/AUDIO, Rg=10k 43 -13.4 Symbol Condition min typ
AN6472NFBP
max 47 -9.4 2.5 215 63.0
Unit dB dBm mVrms A mVrms
45 -11.4 0.8 180 50.0
29.8 0.45
31.8 1.2
dB mVrms
4.8 0.025 6 6 0.5 7 7
V V dB dB
12 - 0.5 20 18 18 0 21.4 19.2 0 0
13 0.5 21.5 19.5 19.5 1.0 22.9 20.7 1.0 1.0
dB dB dB dB dB dB dB dB dB dB
Note) Unless otherwise specified, external supply voltage VCC=5V, line current IL= 0mA, input signal frequency=1 kHz, control voltage V-DOC=high, and control voltage V-DMC = high. *1 Each amp. gain is measured from AUX OUT or MIX OUT to its output (the AUX or MIX preamp. gain is not included in the calculation). *2 The difference from the receiver output gain (Gv-RO).
7
AN6472NFBP
s Electrical Characteristics (cont.) (Ta=252C)
Parameter Link SW Input MIC input gain*1 Rec. input gain*1 Intercom input gain RF1 input gain RF2 input gain SP link input gain Link Maximum Output SP OUT max. output DH OUT max. output RF1 OUT max. output RF2 OUT max. output L-REC OUT max. output Vo - SP Vo - DH Vo - RF1 Vo - RF2 Vo - LR Input L-SP IN, THD=5% L-SW (h02)= ON Input RF1 IN, THD=5% L-SW (h23)= ON Input RF2 IN, THD=5% L-SW (h25) = ON Input RF1 IN, THD=5% L-SW (h2C)= ON Input AUX IN, THD=5% L-SW (h3E)= ON 0 0 0 0 0 Gv - MI Gv - RI Gv - DHI Gv - RF1I Gv - RF2I Gv - SPI Vin= -38dBm, rec. output L -SW(h0E)= ON Vin= -42dBm, rec. output L-SW (h16)= ON Vin= -30dBm, rec. output L-SW (h1E)= ON Vin= -30dBm, rec. output L-SW (h26)= ON Vin= -30dBm, rec. output L-SW (h2E)= ON Vin= -30dBm, SP rec. output L-SW (h02)= ON -1 -1 5 -1 -1 11 Symbol Condition min
ICs for Telephone
typ
max
Unit
0 0 6 0 0 12
1 1 7 1 1 13
dB dB dB dB dB dB
4 4 4 4 4
dBm dBm dBm dBm dBm
Note) Unless otherwise specified, external supply voltage VCC=5V, line current IL= 0mA, input signal frequency=1 kHz, control voltage V-DOC= high, and control voltage V-DMC= high. *1 Each amp. gain is measured from MIC OUT or R PRE OUT to its output.
s Electrical Characteristics (cont.) (Ta=252C)
Parameter Controls Dial mute high level voltage Dial mute high level control current Dial mute low level voltage Dial mute low level control current DC voltage control high level voltage DC voltage control high level control current DC voltage control low level voltage DC voltage control low level control current VDMC - H IDMC - H VDMC - L IDMC - L VDCC - H IDCC - H VDCC - L IDCC - L V- DCC= 0V V - DCC= 5V V- DMC= 0V V- DMC = 5V 2 15 - 0.2 - 40 2 10 - 0.2 -2 - 0.1 25 -20 38 VCC + 0.2 80 0.3 -10 VCC + 0.2 50 0.4 V A V A V A V A Symbol Condition min typ max Unit
Note) Unless otherwise specified, VCC=5V, and IL = 20 mA.
8
ICs for Telephone
s Electrical Characteristics (cont.) (Ta=252C)
Parameter Data input high level voltage Data input high level control current Data input low level voltage Data input low level control current Power Supply Block AC impedance (I) AC impedance (E) Input impedance BT amp. input impedance ALC amp. input impedance Intercom preamp. input impedance RF1 preamp. input impedance RF2 preamp. input impedance SP input impedance Zin - BT Zin - ALC Zin - DH Zin - RF1 Zin - RF2 Zin - SP Pin 17 Input Pin 40 Input Pin 56 Input Pin 57 Input Pin 58 Input Pin 42 Input 8.7 8.5 8.5 8.5 8.5 37.5 ZAC - I ZAC - E IL=80mA, VCC= 0V, Vin=200mVrms, Fin=1kHz IL=80mA, VCC=5V, Vin=200mVrms, Fin=1kHz 450 450 Symbol VDIN - H IDIN - H VDIN - L IDIN - L V- DIN = 0V V- DIN=5V Condition min 2 70 - 0.2 -1 typ
AN6472NFBP
max VCC + 0.2
Unit V A V A
160
250 0.3
- 0.1
570 580
750 750

9.5 9.5 9.5 9.5 9.5 50.0
10.7 10.5 10.5 10.5 10.5 62.5
k k k k k k
s Electrical Characteristics (Design Values for Reference) (Ta=252C) The following are design values for reference, not guaranteed values.
Parameter Speech Block Rec. output noise voltage (I) Rec. output noise voltage (E) Trans. output noise voltage (I) Trans. output noise voltage (E) Dial mute trans. amp. mute attenuation Vn - IR Vn - ER Vn - IT Vn - ET M - TDM IL=30mA, VCC=0V, DIN/AUDIO IL=30mA, VCC=5V, DIN/AUDIO IL=30mA, VCC=0V, DIN/AUDIO IL=30mA, VCC=5V, DIN/AUDIO IL=30mA, VCC=5V, Vin= -30dBm, V- DBM-H/L IL=30mA, Vin= -30dBm, VCC=5V, Lsw (h3F)=OFF/ON IL=30mA, Vin= -30dBm, VCC=5V, Lsw (h27)= OFF/ON Pin 12 Input Pin 21 and 22 Input IL= 0mA, VCC=5V, and ALC output distortion2% IL=0mA, VCC=5V, and Vin= -45dBm to -20dBm VCC=5V, Vin= -10dBm IL= 0mA, and LSW (h07)= ON/OFF 0.3 0.3 0.3 0.3 75 mVrms mVrms mVrms mVrms dB Symbol Condition min typ max Unit
Trans. preamp. mute attenuation
M - TM
70
dB
Rec. output mute attenuation Rec. preamp. input impedance MIC preamp. input impedance REC/PLAY Block ALC amp. ALC width ALC amp. ALC effect Rec. amp. mute attenuation
M - RO Zin - R Zin - M
50 500 500
dB k k
W - ALC DALC M - REC
40 1 80
dB dB dB
9
AN6472NFBP
ICs for Telephone
s Electrical Characteristics (Cont.) (Design Values for Reference) (Ta=252C) The following are design values for reference, not guaranteed values.
Parameter EQ amp. mute attenuation Rec. preamp. input impedance EQ amp. input impedance VOX amp. input impedance Link Switch Link SW mute attenuation MIX preamp. input impedance AUX preamp. input impedance CPC output impedance Noise reduction amp. input impedance VOX cross talk M-LS Zin-MIX Zin-AUX Zout-CPC Zin-NL VOX-CT VCC=5V, IL=30mA, AC output measured at link ON/OFF Pin 53 input Pin 55 input Pin 25 input Pin 9 input VCC=5V, IL=30mA, cross talk to line during VOX 75 500 500 100 45 -70 dB k k k dBm Symbol M-EQ Zin-REC Zin-EQ Zin-VOX Condition VCC=5V, Vin= -30dBm IL= 0mA, LSW(h0F)=ON/OFF Pin 43 input Pins 47 and 48 input Pin 47 input min typ 80 10 500 500 max Unit dB k k k
s Pin Descriptions
Pin No. Pin name I/O 1 GND Waveform
0V
Description Ground : *This is the ground pin for the speech network. Line power input: *Connects to the positive output of the diode bridge.
Equivalent circuit GND for REC/PLY, VREG, SPEECH and LINK
Remarks
2
VL
I
DC 3 10V
2
TO
3
ST
O
DC 0.3V
Side-tone adjustment: *Grounded through R1 (27) *Connects to the side-tone adjusting circuit to adjust side tone and receiver level. Line voltage control (1) : Int. ref. voltage output (2) : *Output impedance=50
24k
3
The line drive gain (G) is : G = ZLine//ZTel R1 Also assuming ZLine600 ZTel 600 R1= 27 G= 20log 300 = 20.9db 27 C2 and the internal resistance determine the f. characteristics.
4 5
VL- CONT Vref- SN
I O
DC1V 1V (Const)
61 Vreg
Int. ref. voltage output (1) : 6 Vref O
1V (Const)
6
+
*Outputs half the Vreg reference voltage. Trans. preamp. output : *C7 as connected between this pin and the ground forms a low-pass filter.
24 k
-
5
Grounded through 0.01F capacitor.
a
4
7
T- FILTER
O
6k
DC1V
7
Note) The symbols are the same as those used in the application circuit.
10
ICs for Telephone
s Pin Descriptions (cont.)
Pin No. Pin name I/O
Pin 8 output
AN6472NFBP
Waveform
DC (with a capacitor)
Description *Noise reduction detection amp. output : A smoothing capacitor C6 and R5 connect to this pin to adjust the attack and recovery times of noise reduction. *Noise reduction detection amp. input : Noise reduction amp. output is fed through C7 and R6 to this pin. *Noise reduction amp. output : Connects to the noise reduction detection amp. input. Auto. PAD control : *Connects through a resistance to Pin 61(Vreg). If the resistance increases, the PAD operates closer to the near end. If the resistance decreases, the PAD operates closer to the far end. Rec. preamp. input : *Receiver signals are input from the side-tone circuit to this pin. *R8 and C9 connected between Pin 13 and this pin determine the f. characteristics. Rec. preamp. output : *R8 and C9 connected between Pin 12 and this pin determine the f. characteristics. *The output impedance is up to 1 k. Rec. amp. input : Rec. amp. outputs (1 and 2) : *A ceramic or dynamic receiver is connected. *The output circuit is a BTL configuration. *The output impedance is up to 50 . BT signal input : *BT (beep tone) signals are input through C15 to this pin. *Input impedance is 10 k. DTMF preamp. output : *A C/R combination between Pin 19 and this pin determines the f. characteristics of the DTMF preamp. DTMF signal input : *DTMF signals are input through a capacitor to this pin. *DTMF signals are enabled when DMC is low at Pin 40.
Equivalent circuit
Remarks *This pin must be grounded if noise reduction is not used. *The greater C7, the longer the attack time. The smaller R6, the shorter the recovery time. *Noise reduction detection amp. gain (G) is : G = 64K R6
8
VN DET
Input Full-wave detection (with no capacitor)
Vref-SN
+
Vref-SN
+ -
9
VN DET- IN VN OUT
-
I
95k 10
9
64k 8
3k
0.1F
10
O
VREF
11
APC
I
Vreg-R * I IL
11
I I IL
12
RV IN
I
VREF - SN
+
12
-
13
The receiver preamplifier gain (G) is : 1 1 1 R9 + jC9 R8 + jC10
13
RV PREOUT
O
VREF - SN
+ -
10k
13
G= -
14
RV FILTER RV OUT (1)
O
VREF - SN
16
15 * 16
10k
+ -
VREF - SN
O RV OUT (2)
VREF - SN
13
30k
15
Vref-SN 10k
17
+ -
17
BT- IN
I
VREF - SN Signal input
18
MF - OUT
O
VREF - SN
+ -
18
In the application circuit, MIC. IN (-) is input through a capacitor. This capacitor and R12-R14, and C15 and C16 determine the f. characteristics.
Vref-SN 10k
+
19
MF - IN
I
VREF - SN Signal input
19 18
-
The 10 k input impedance and C12 or C13 form a HPF.
11
AN6472NFBP
s Pin Descriptions (cont.)
Pin No. Pin name I/O Waveform Description MIC preamp. output : *R12 and C14 connected between Pin 22 and this pin determine the f. characteristics. *The output impedance is up to 1 k.
21
+ -
ICs for Telephone
Equivalent circuit
Remarks
20
MIC OUT
O
VREF - SN
Vref 10k
+ -
21
MIC IN (+)
I
VREF - SN
MIC preamp. input (1) : *A bias resistor and a microphone connect to this pin.
22
20
22
MIC IN (-)
I
VREF - SN
MIC preamp. input (2) : *R12 and C14 connected between Pin 20 and this pin determine the f. characteristics.
23
DMC
I
Dial mute control : *Normal speech mode when Pin 23 is high or open (MIC amp. ON and rec. amp. ON). *DTMF mode when Pin 23 is low (DTMF amp. ON and BT amp. ON).
VCC
61
200k
23
100k
24
DC - CONT
I
0.2V Line DC voltage
L-VCC
25
CPC
O
0.2V Line interruption
Line voltage control : *Line voltage is normal when the input voltage at this pin is high. Line voltage increases by 1-1.5 V when the input voltage is low. Line interruption detector output : *This is an open collector output to a microprocessor, requiring a pull-up resistor connected to the microprocessor's power supply. This pin goes low when line voltage is 3.0 V or more, and goes high when 1.5 V or less. Strobe signal input : *The strobe signal for serial control data is input to this pin. The rising edge of the strobe signal determines the timing at which internal control address or ON/OFF status is validated. Clock signal input : *The clock signal for serial control data is input to this pin. The rising edge of the clock signal determines the timing at which data is read. Data input : *Serial data is input to this pin. Data is read into the internal shift register in synchronization with clock signals.
150k
24
200k
VL 2 144k 56k
L-VCC 100k
25
26
L-VCC
5V
26
STR
I
0V
10k 300k
27
L-VCC
5V
10k 300k
27
CLK
I
0V
28
L-VCC
5V
10k 300k
28
DATA
I
0V
12
ICs for Telephone
s Pin Descriptions (cont.)
Pin No. Pin name I/O 29 GND Waveform Description Ground : *This is the ground pin for the logic circuits. Logic power supply input :
L * VCC
AN6472NFBP
Equivalent circuit
Remarks
30
L- VCC
31
VOX- OUT
O
0V Voice ON
VOX detector output : *This is an open collector output. *This pin goes high when voice signals are input to Pin 37. Loudspeaker link output : *This is a link switch output to an external loudspeaker amplifier. *The output amplifier gain is selectable between 12 and 0 dB. *Output impedance is 50 30. RF2 link output : *This is a link switch output. *Output impedance is 50. RF1 link output : *This is a link switch output. *Output impedance is 50.
31
Vref - SN From LINK SW
+
0/12dB
50k
32
32
SP- OUT
O
VREF - SN
10k Vref
30k
When address 2F of the cross-point switch is OFF, the output amplifier gain is set to 12 dB.
-
33
RF2- OUT
O
VREF - SN
Vref- SN From LINK SW
+ -
50k
33 34
34
RF1- OUT
O
VREF - SN
10k
68k
35
DH- OUT
O
VREF - SN
Intercom link output : *This is a link switch output to an intercom. *Output impedance is 50.
From LINK SW
+ -
Vref - SN 50k
35
10k
90k
Pin 36 output
DC (with a capacitor)
36
VOX DET
O
Pin 37 input
Half-wave rectification (with no capacitor)
VOX detection control : *A smoothing capacitor (C18) and a resistor (R18) connect in parallel to this pin to adjust the attack and recovery times of the VOX detector.
37
Vref-PR
+ -
VOX detection can be done in two ways : A) With small C18 (560 pF) and small R18 (39k) VOX input VOX output
500
36
500
37
VOX IN
I
VOX amp. input : *VOX (voice detection) signals are input to this pin. *Input impedance is 500.
B) With large C18 (22 F) and large R18 (100 k) VOX input VOX output
38
LTS- OUT
O
VREF - SN
Time stamp link output : *This is a buffered link switch output. *Output impedance is 50. Recording link output : *This is a buffered link switch output. *Output impedance is 50.
From LINK SW
+ -
38 39
39
LRC- OUT
O
VREF - SN
13
AN6472NFBP
s Pin Descriptions (cont.)
Pin No. Pin name I/O ALC. IN Waveform Description ALC input : *Pin 45 connects through a coupling capacitor to this pin. *Input impedance is 10k.
40
Pin 41 output
DC (with a capacitor)
ICs for Telephone
Equivalent circuit
Remarks
40
I
Vref - PR
+ -
VRE G
41
ALC. DET
O
Input
Full-wave rectification (with no capacitor)
ALC detection control : *A smoothing capacitor (C20) and a resistor (R20) connect in parallel to this pin to adjust the attack and recovery times of the ALC. Loudspeaker link input : *SP signals to this pin are output through a coupling capacitor to the link switch. *Input impedance is 50k. Recording input : *Recording signals are input through a coupling capacitor to this pin. *Input impedance is normally 10k. It decreases during ALC operation. Recording preamp. inverse input : *A/CR combination between Pin 45 and this pin determines the gain and f. characteristics of the recording preamplifier. Recording preamp. output : *Outputs amplified recording signals. *Output impedance is 50. Recording bias current control : *A C/R combination connected to this pin determines the recording bias current and gain of a recording head. *The smaller the resistance of the C/R combination, the greater the bias current and gain. To recording head : *A recording head connects to this pin. EQ amp. inverse input : *A C/R combination between Pin 49 and this pin determines the equalizer characteristics. EQ amp. output : *Outputs amplified equalizer signals. *Output impedance is 50. REC/PLAY int. ref. voltage output : *The Pin 5 ref. voltage is buffered and output from this pin. *Output impedance is 50
Vref - SN
+ -
2k
41
*Ground Pin 41 if no ALC circuit is used. *The larger C20, the longer the attack time. The smaller R20, the shorter the recovery time
42
SP - IN
I
VREF - SN
to LINK SW
42
50k
Vref-PR 10k
43
+ -
43
RD PRE - IN
I
VREF - SN
50k 22k from ALC
44
RD PRE - NF REC PRE - OUT
I
VREF - SN
+ -
45
The gain (G) of the recording preamplifier is : G=- R23 R22+jC23
44
45
O
VREF - SN
46
BIASS ADJ
61
VREG
VREF - PR
45
+ -
*Address 07 of the crosspoint SW determines the ON/OFF status of the rec. preamp. *The bias current to the head is : IH = VREF-PR x3 R25 1 Vreg VREF-PR = 2
Bias voltage
47
HEAD I/O
0V During recording 0V During playing
46
47
48
EQ. NF
I
VREF - PR
Vref- PR
from recording head
48
+ -
49
49
EQ. OUT
O
VREF - PR
*The gain of the equalizer amp. is calculted the same way as the receiver preamp. *Address OF of the crosspoint SW determines the ON/OFF status of the EQ amp.
50
VREF - PR
O
1 V 2 REF (CONST)
Vref 6
+ -
50
51
GND
Ground :
14
ICs for Telephone
s Pin Descriptions (cont.)
Pin No. Pin name I/O MIX OUT Waveform Description MIX preamp. output : * A C/R combination between Pin 53 and this pin determines the gain and f. characteristics of the MIX preamp. * Output impedance is 50. MIX link input : * MIX signals are input through a coupling capacitor to this pin. AUX preamp. output : * A C/R combination between Pin 55 and this pin determines the gain and f. characteristics of the AUX preamp. * Output impedance is 50. AUX link input : * AUX signals are input through a coupling capacitor to this pin. Intercom link input : * Intercom signals are input through a coupling capacitor C30 to this pin. * Input impedance is 10k RF1 link input : * RF1 signals are input through a coupling capacitor C31 to this pin. * Input impedance is 10k. RF2 link input : * Same as above. Power-ON reset control : * C33 between this pin and GND determines the powerON reset time of the logic circuits.
5V 57/58
AN6472NFBP
Equivalent circuit
Vref-SN to LINK SW
+ -
Remarks
52
O
VREF - SN
53
MIX IN
The gain of the MIX preamp. is calculated the same way as the rec. preamp.
I
53
52
Vref-SN to LINK SW
+ -
54
AUX OUT
O
VREF - SN
55
AUT IN
The gain of the AUX preamp. is calculated the same way as the rec. preamp.
I
55
54
Vref-SN 10k
56
+ -
56
DH IN
I
VREF - SN
to LINK SW
57
RF1 IN
Vref-SN 10k
+ -
I
VREF - SN
The input impedance as illustrated left and C30, C31, or C32 form a HPF.
to LINK SW
58
RF2 IN
I
VREF - SN
VCC 50k Comparator
59
+ -
59
PR
I
150k
Reset signal
*The larger C33, the longer the power-ON reset time. * The power-ON reset signal is output when the supply voltage reaches 4V.
60
VCC
0.5V
External supply voltage input : * -50.5V power supply is input to this pin. Internal supply voltage output : * A power supply derived from line voltage is output from this pin to the internal speech network.
2
VL
61
61
Vreg
VCC to 0.2V
O
DC 2V during power failure
2
64
62
VLC
2 to 5 VDC depending on VL
Circuit voltage control (2) : *This pin is grounded through C36.
62
C36 (typically 47F) determines how the circuit voltage fluctuates.
63 2 VL
63
PD2
DC
O
0 to 3 V depending on VL
Power supply
Line current bypass : *Line current is bypassed from this pin through R35 to GND. R35 must be 1/2 W or more.
33
64
ZTel is 1.5-2.0k on the IC side. It must be adjusted to 600 by inserting a 820 resistor between VL and GND.
64
R36 33 820 100F
DC
64
PD1
I
Same as above VL-33 x IL
Line current bypass (1) : * Line current is bypassed from this pin through R36 to Pin 2. R36 must be 1/2 W or more.
VL
63
15
15
AN6472NFBP
Logic Specifications s Basic Block Diagrams
Output (cross-point SW and other controls)
ICs for Telephone
Latch Circuit
Decoder Decoder (6 bit, 48 channels)
Reset
Shift Register A6 A5 A4 A3 A2 A1 D
Clock
Data
Strobe
s Time Charts (Assuming the address h26 latch is to be set)
Clock
Data
1 (A6)
0 (A6)
0 (A4)
1 (A3)
1 (A2)
0 (A1)
1 (D)
Strobe
1. Data is read into the shift register in synchronization with a rising edge of the clock, with the higher data being shifted sequentially on a first-come highest-bit basis. 2. When the strobe is low, data is shifted sequentially on the sift register in synchronization with the clock. Data on the latch circuit will not change. 3. When the strobe goes high, the latched data whose address is represented by the highest six bits of the shift register is updated. Latched data is set when the least significant bit is 1, and reset when the bit is 0. 4. Referring to 3 above, if the address is h00 (the highest six bits of the shift register are all 0s), the latch circuit is cleared (all reset) regardless of the data content. 5. At power-on (VCC ON), the latch circuit is cleared (by power-ON reset).
16
ICs for Telephone
s Logic Circuits Address Specifications
1. Cross-point switch Output Input Loudspeaker Microphone Receiver Intercom RF1 RF2 MIX AUX 10 18 20 28 30 38 21 29 31 39 32 3A 09 Handset rec. Line ouput Loudspeaker 02 0A 12 1A 23 2B 33 3B 2C 34 3C 35 3D 0B 0C 14 1C 0D 15 1D 25 Intercom RF1 RF2
AN6472NFBP
Recording
Time stamp
0E 16 1E 26 2E 37 3E
Note) Empty space means "not applicable." Address is in hexadecimal.
2. Other control switches Address 00 07 0F 17 1F 27 2F 3F 09, 21, 29
Description Cross-point SW all reset Recording amp. ON Playing amp. ON Receiver volume 6 dB up Receiver volume 9 dB up Handset receiver amp. mute SP output amp. gain 12 dB down MIC preamp. mute Receiver noise reduction is enabled.
Note) Address is in hexadecimal.
17
AN6472NFBP
s Timing Charts
1/fCLK tWh (CLK) tWL (CLK)
ICs for Telephone
90% 2.5V CLK 10% tr (CLK)
90% 2.5V 10% 2.5V
tf (CLK)
DATA 2.5V 2.5V
tsu (DATA)
th (DATA)
tsu (STB) STR
th (STB)
2.5V
2.5V
tW (STB)
PD --Ta
1,600
Power Dissipation PD (mW)
1,400 1,200 1,000 900mW 800 600 400 200 0 0 25 50 75 100 125 150 640mW
Ambient Temperature Ta (C)
18
PLAY IN REC OUT JP8 JP5 JP7 JP6 JP4 C19 0560pF C23 0.01F DH. OUT RF1. OUT C24 22F RF2. OUT VOXIN ALC IN
REC IN LINK-SP IN
RPRE IN LINK-R OUT
R27 1k
C26 1F
R25 47
R24 1k
R22 10k
+
R28
R19
C18
200 C26 22F
R20 220k
+
C20 22F
R21 C22 0.15F 10k C21 0.1F
C25 0.47F R27 1k
C39 0.068F
TS OUT
10k 0.033F
R18 10k
AN6472NFBP
R30
330k
C27 0.01F
R29 10k
48
EQ OUT
+
49 L(07)
COMP 10dB
-
+
L(07) 31 R17 120k 30
50
PV-VREF
C27 100F
Vref ALC INJ.
L(2F)
0/12 dB 20 dB 18 dB 18 dB 0dB 0dB
51 29
s AN6472NFBP Applicant Circuit
MIX OUT
0dB
52 28 27 26 25
R31
MIX IN
20k
R33 10k
53
-
C28 0.068F
AUX OUT
54
R32
AUX IN
20k
55
-
STR CPC 100k 24 R16 100k 23 VCC
R34 10k
C29 0.068F
DH IN
56
6dB
C30 0.068F
Decorder
57
Latch
RF1 IN
0dB
C31 0.068F
DC Contorol DM Contorol
+ -
SW1 SW2
Data Input CLK VCC VREG MIC 22 R14 10k C16 0.068F 21 MIC IN+
MICOUT
RF2 IN DCC
58
0dB
C32 0.068F
59
C33 47F C34 100F
60
P.O.R AP
0dB 0dB
VREG Noise Protector DMC Vcc
0dB
C35 100F
61
Power Supply Control
62 DMC
-
Power Interruption Detector AP Noise Control
+ 30dB
Detection
Vcc DMC DMC L(17) L(1F)
- 0dB
+
R10
C36 47F R35
10k
63
15
15 R36
33
64
1
+
2
3
4
5
GND R1 27
+ +
R6 10k
C7 0.1F
R2 470
C2 22F
C4 100F
C3 0.01F
C5 0.01F
R5 100k
C8 0.1F
R8 12k
JP2
C6 10F
R37 820 R3 4.7k JP1
C1 0.022F
R7 6.8k
C37 + 100F
C10 0.068F
R4 7.7k
R5 12k VREF Rin
-
+
19
47 46 R23 56k 45 44 43 42 41 40 39 38 37 36 35 34 33
ALC Detector VOX Detector
32 SP OUT
+
VOX OUT LOGIC VCC C17 100F LOGIC GND DATA
+
+
+ 0dB
D a1 a2 a3 a4 a5 a6
L(3F)
0dB
+
+
20
0dB
R12 27k C14 0.0015F 19 18
R13 C15 10k 4.7F
MIC IN- DTMF IN R11 10k C13 0.068F
R15 2.2k
+
Vref
AP Control
0/6/9dB
L(27)
DTMF OUT 17 C12 0.068F BT IN
6
7
8
9
10
11
12
13 C9 0.001F R9 47k
14
15
16
Rout1
C38 0.1F RFILTER SP Rout
ICs for Telephone
Rout2
JP3

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